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Freescale Semiconductor, Inc.
Technical Data
TANGO3 MC33493/D Rev. 1.6, 6/2002 PLL tuned UHF Transmitter for Data Transfer Applications
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FEATURES
* * * * * * * * * * * Selectable frequency bands: 315-434MHz and 868-928MHz OOK and FSK modulation Adjustable output power range Fully integrated VCO Supply voltage range: 1.9-3.6V Very low standby current: 0.1nA @ TA =25C Low supply voltage shutdown Data clock output for microcontroller Extended temperature range: -40C to 125C Low external component count Typical application compliant with ETSI standard
PIN CONNECTIONS
DATACLK DATA BAND GND XTAL1 XTAL0 REXT
1 2 3 4 5 6 7
14 13 12 11 10 9 8
MODE ENABLE VCC GNDRF RFOUT VCC CFSK
Ordering Information Device
MC33493 DTB
Ambiant Temperature Range
-40C to 125C
Package
TSSOP14
Figure 1: Simplified block diagram
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc., 2002
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PIN FUNCTION DESCRIPTION
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PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name DATACLK DATA BAND GND XTAL1 XTAL0 REXT CFSK VCC RFOUT GNDRF VCC ENABLE MODE Description Clock output to the microcontroller Data input Frequency band selection Ground Reference oscillator input Reference oscillator output Power amplifier output current setting input FSK switch output Power supply Power amplifier output Power amplifier ground Power supply Enable input Modulation type selection input
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Voltage Allowed on Each Pin ESD HBM Voltage Capability on Each Pin (note 1) ESD MM Voltage Capability on Each Pin (note 2) Storage Temperature Junction Temperature
Notes: 1 Human Body model, AEC-Q100-002 Rev. C. 2 Machine Model, AEC-Q100-003 Rev. E.
Symbol VCC
Value VGND - 0.3 to 3.7 VGND - 0.3 to VCC + 0.3 2000 150
Unit V V V V C C
Ts Tj
-65 to +150 +150
TRANSMITTER FUNCTIONAL DESCRIPTION
MC33493 is a PLL tuned low power UHF transmitter. The different modes of operation are controlled by the microcontroller through several digital input pins. The power supply voltage ranges from 1.9V to 3.6V allowing operation with a single lithium cell.
PHASE LOCKED LOOP AND LOCAL OSCILLATOR
The VCO is a completely integrated relaxation oscillator. The Phase Frequency Detector (PFD) and the loop filter are fully integrated. The exact output frequency is equal to: fRFOUT = fXTAL x [PLL Divider Ratio]. The frequency band of operation is selected through the BAND pin. Table 1 provides details for each frequency band selection.
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MC33493 Technical Data
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RF OUTPUT STAGE
Table 1: Band selection and associated divider ratios BAND Input Frequency PLL Divider Crystal Oscillator Level Band (MHz) Ratio Frequency (MHz) 315 9.84 High 32 434 13.56 Low 868 64 An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the RF output stage is disabled.
RF OUTPUT STAGE
The output stage is a single ended square wave switched current source. Harmonics are present in the output current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical application demonstrates compliance to ETSI standard. A resistor Rext connected to the REXT pin controls the output power allowing a trade-off between radiated power and current consumption. The output voltage is internally clamped to Vcc 2Vbe (typ. Vcc 1.5V @ TA=25C).
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MODULATION
A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output stage state: DATA=0 output stage off, DATA=1 output stage on. If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel. The logic level applied on pin DATA controls the state of this internal switch: DATA=0 switch off, DATA=1 switch on. DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty cycle cannot exceed 1 reference period (75ns for a 13.56MHz crystal). This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation multiplied by the PLL Divider Ratio (see table 1).
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MICROCONTROLLER INTERFACE
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Figure 2: Crystal pulling configurations
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MICROCONTROLLER INTERFACE
Four digital input pins (ENABLE, DATA, BAND and MODE) enable the circuit to be controlled by a microcontroller. It is recommended to configure the band frequency and the modulation type before enabling the circuit. One digital output (DATACLK) provides to the microcontroller a reference frequency for data clocking. This frequency is equal to the crystal oscillator frequency divided by 64 (see table 2). Table 2: DATACLK frequency vs crystal oscillator frequency Crystal Oscillator Frequency (MHz) DATACLK Frequency (kHz) 9.84 154 13.56 212
STATE MACHINE
Figure 3 details the state machine.
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MC33493 Technical Data
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STATE MACHINE
Figure 3: State machine Power ON AND ENABLE=0
State 1 Standby mode
ENABLE=0
ENABLE=1
ENABLE=0
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State 2 PLL out of lock-in range No RF output PLL in lock-in range PLL out of lock-in range
State 4 Shutdown mode
Vbattery < Vshutdown
State 3 Transmission mode State 1: The circuit is in standby mode and draws only a leakage current from the power supply. State 2: In this state, the PLL is out of the lock-in range. Therefore the RF output stage is switched off preventing RF transmission. Data clock is available on pin DATACLK. Each time the device is enabled, the state machine passes through this state. State 3: In this state, the PLL is within the lock-in range. If tMOTOROLA
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POWER MANAGEMENT
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Figure 4: Signals waveforms and timings definition ENABLE DATACLK tDATACLK_settling > tPLL_lock_in tPLL_lock_in DATA MODE=0 (OOK) RFOUT MODE=1 (FSK) fhigh State 1 State 2 fcarrier flow fhigh State 3 fcarrier flow fhigh State 1
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: PLL locked
POWER MANAGEMENT
When the battery voltage falls below the shutdown voltage threshold (VSDWN) the whole circuit is switched off. It has to be noted that after this shutdown, the circuit is latched until a low level is applied on pin ENABLE (see state 4 of the state machine).
DATA CLOCK
At start-up data clock timing is valid after the data clock settling time. As clock is switched off asynchronously, the last period duration cannot be guaranteed.
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MC33493 Technical Data
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40C;+125C], Rext=12k+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output load RL=50+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics: figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25C. Limits Parameter 1 1.1 Test Conditions, Comments Min. General Parameters TA25C Supply Current in Standby Mode TA=60C TA=85C TA=125C 315 & 434 bands, OOK and FSK modulation, continuous wave, TA=25C 315 & 434 bands, DATA=0, -40CTA125C Supply Current in Transmission Mode 868MHz band, DATA=0, -40CTA125C 315 & 434 bands, OOK and FSK modulation, continuous wave, -40CTA125C 868MHz band, OOK and FSK modulation, continuous wave, -40CTA125C Supply Voltage TA=-40C TA=-20C Shutdown Voltage Threshold TA=25C TA=60C TA=85C TA=125C 0.1 7 40 800 11.6 5 30 100 1700 13.5 nA nA nA nA mA Typ. Max. Unit
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1.2 1.3 1.4 1.7
1.5 1.6
-
4.4 4.6
6.0 6.2
mA mA
1.8
-
11.6
14.9
mA
1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16
-
11.8 3 2.04 1.99 1.86 1.76 1.68 1.56
15.1 3.6 2.11 2.06 1.95 1.84 1.78 1.67
mA V V V V V V V
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ELECTRICAL CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40C;+125C], Rext=12k+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output load RL=50+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics: figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25C. Limits Parameter 2 2.1 Rext value 315 & 434MHz bands, with 50 matching network 868MHz band, with 50 matching network Output Power 2.4 2.8 Current & Output Power Variation vs. Rext value 315 & 434MHz bands, -40CTA125C 868MHz band, -40CTA125C 315 & 434MHz bands, with 50 matching network 315 & 434MHz bands, with 50 matching network Harmonic 2 Level 868MHz band, with 50 matching network 315 & 434MHz bands 868MHz band 315 & 434MHz bands, with 50 matching network Harmonic 3 Level 868MHz band, with 50 matching network 315 & 434MHz bands 868MHz band Spurious Level @ fcarrier f DATACLK Spurious Level @ fcarrier f reference Spurious Level @ fcarrier/2 315 & 434MHz bands 868MHz band 315 MHz band 434MHz band 868MHz band 315MHz band 434MHz band 868MHz band Test Conditions, Comments Min. RF Parameters 12 -3 -7 5 1 0 -3 -0.35 -0.25 -34 -49 -23 -38 -32 -57 -21 -48 -36 -29 -37 -44 -37 -62 -80 -45 21 3 0 k dBm dBm dBm dBm dB/k mA/ k dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Typ. Max. Unit
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2.2 2.3
2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.41 2.26 2.27
-
-17 -27 -15 -39 -24 -17 -30 -34 -27 -53 -60 -39
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MC33493 Technical Data
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40C;+125C], Rext=12k+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output load RL=50+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics: figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25C. Limits Parameter Test Conditions, Comments Min. 2.30 Phase Noise 2.31 315 & 434MHz bands, 175kHz from f carrier 868MHz band, 175kHz from f carrier fcarrier within 30kHz from the final value, crystal series resistor=150 OOK modulation FSK modulation 75 315 & 434MHz bands, see note 1 868MHz band, see note 1 MODE=0, DATA=x MODE=1, DATA=0 MODE=1, DATA=1 CFSK Output Capacitance Data Rate Manchester coding MODE=0, see note 2 MODE=1, see note 2 50 -
Unit Typ. -75 -73 400 1 20 20 90 70 90 1 5.25 Max. -68 -66 1600 200 50 100 200 300 10 7.5 200 dBc/ Hz dBc/ Hz s pF dBc kHz kHz k pF kBit/s s ns
-
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2.32 2.33 2.34 2.44 2.35 2.36 2.37 2.38 2.39 2.43 2.40 2.41
PLL Lock-in Time, tPLL_lock_in XTAL1 Input Capacitance Crystal Resistance OOK Modulation Depth FSK Modulation Carrier Frequency Total Deviation CFSK Output Resistance
Data to RF delay difference between falling and rising edges, 2.42 tdelay_difference
3.5 -200
Note 1: This parameter is depending on crystal characteristics, load capacitor values (see Table 6) and PCB track capacitance. Note 2: Delay difference definition Input data Demodulated data tdelay_rise tdelay_fall
From 50% of data edge to corresponding demodulated signal envelope edge: tdelay_difference=tdelay_fall-tdelay_rise
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RF OUTPUT SPECTRUM
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40C;+125C], Rext=12k+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output load RL=50+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics: figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25C. Limits Parameter 3 3.1 Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Current ENABLE Pull Down Resistor DATACLK Output Low Voltage Cload = 2pF 3.7 3.8 3.9 3.10 DATACLK Output High Voltage DATACLK Rising Time DATACLK Falling Time DATACLK Settling Time, tDATACLK_settling Cload = 2pF, measured from 20% to 80% of the voltage swing 45% < Duty Cycle fDATACLK < 55% Pins BAND, MODE, DATA = 1 Pins BAND, MODE, ENABLE, DATA Test Conditions, Comments Min. Microcontroller Interfaces 0 0.7 x VCC 0 0.75 x VCC -
Unit Typ. Max.
180 250 150 800
0.3 x VCC VCC 120 100 0.25 x VCC VCC 500 400 2000
V V mV nA k V V ns ns s
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3.2 3.3 3.4 3.5 3.6
RF OUTPUT SPECTRUM
Following are spectrums of transmitter carrier, measured in conduction mode. Three different spans have been used. The 5MHz span spectrum (figure ) shows phase noise response close to the RF carrier, and the noise suppression within the PLL loop bandwidth. The 50MHz span spectrum (figure 6) shows both phase noise and reference spurious. Finally figure 7 shows second and third harmonics of carrier. All these spectrums are measured in OOK modulation, at DATA=1. Figure 8 shows spectrum in case of FSK modulation, with 45kHz deviation, at 4kbit/s data rate.
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MC33493 Technical Data
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RF OUTPUT SPECTRUM Figure 5: RF spectrum at 434MHz frequency band displayed with a 5MHz span
Resolution bandwidth: 100kHz Resolution bandwidth: 30kHz
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Figure 6: RF spectrum at 434MHz frequency band displayed with a 50MHz span
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RF OUTPUT SPECTRUM
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Figure 7: RF spectrum at 434MHz frequency band displayed with a 1.5GHz span
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Figure 8: RF spectrum at 434MHz band for a 70kHz FSK deviation at 4.8kbit/s
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MC33493 Technical Data
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OUTPUT POWER MEASUREMENT
OUTPUT POWER MEASUREMENT
The RF output levels given in the electrical characteristics section are measured with a 50 load directly connected to the pin RFOUT as shown below in figure 9. This wideband coupling method gives results independent of the application. Figure 9: Output power measurement configurations VCC
Impeder: TDK MMZ1608Y102CTA00
RFOUT
100pF
RF output
RL=50
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The configuration shown in figure 10-a provides a better efficiency in terms of output power and harmonics rejection. Schematic on figure 10-b gives the equivalent circuit of the pin RFOUT and the DC bias impeder as well as the matching network components for 434MHz frequency band. Figure 10: Output model and matching network for 434MHz band VCC
Impeder: TDK MMZ1608Y102CTA00
RFOUT (a)
Matching Network
RF output
RL=50
Matching Network
(b)
L1 39nH C0 R0 Ri
3k
C3 330pF
50
RL Load
1.5pF 250 RFOUT pin
Impeder
Figure 11 gives the output power versus the Rext resistor value with 50 load and with matching network.
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR OOK MODULATION
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Figure 11: Output power at 434MHz band vs Rext value
Output power measurement in typical conditions (434MHz - Vcc=3V - 25C)
REXT SPECIFIED RANGE
8
6
Output power when matched (dBm) -0.35dB/k # -0.35mA/k
4
2 RFOUT Level (dBm) 0
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-2
-4
Output power on 50 load (dBm)
-6 6 9 12 15 Rext (k) 18 21 24
The 50 matching network used for the 868MHz band is similar to the 434MHz, except components values: in figure 10b, L1 is changed to 8.2nH and C3 to 470pF. The typical gain of this 868MHz matching network is 4dB compared to unmatched configuration.
COMPLETE APPLICATION SCHEMATIC AND PCB FOR OOK MODULATION
Figure 12 gives a complete application schematic using a Motorola MC68HC908RK2 microcontroller. OOK modulation is selected, fcarrier= 433.92MHz. C2 to C5 capacitors can be removed if switches debounce is done by software. Figure 12: Application schematic for OOK modulation, 434MHz frequency band
Vbat
Vbat
LED1
SW1
SW1a
SW2
SW2a
Note that for 868MHz band application, the input pin BAND must be wired to ground. See component description
1
B1
C2
R1 750
C3
C4
C5
2
1
2
3
4
5
6
7
8
9
10
2.2nF
2.2nF
2.2nF
2.2nF
Vbat
U1
1
2
3
DATACLK
DATA
BAND
GND
XTAL1
XTAL0
REXT
MODE
14
C7
22nF
ENABLE
13
VCC
12
U2
PTA0
PTB0/MCLK
PTB1
PTB2/TCH0
PTB4/TCH1
PTB5
PTB3/TCLK
OSC1
OSC2
VSS
PTA1/KBD1 20
C6 8.2pF
Y1
4
5
GNDRF
11
PTA2/KBD2
19
RFOUT
10
6
PTA3/KBD3
18
13.56MHz
7
VCC
9
PTA4/KBD4
17
CFSK
8
C9 2.2pF
R2 12K
MC33493
PTA5/KBD5
16
C8 100pF
PTA6/KBD6
15
PTA7
14
RST
13
IRQ1
12
VDD
11
Vbat
C10 100nF
MC68HC908RK2
14
MC33493 Technical Data
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION on following tables 3 and 4. Component Y1 Table 3: External components description for OOK Function Value 315MHz band: 9.84 Crystal, 434MHz band: 13.56 see table 4 868MHz band: 13.56 RF output level setting 12 resistor (Rext) Crystal load capacitor Power supply decoupling capacitors 8.2, see note 3 22 100 Unit MHz MHz MHz k pF nF pF
R2 C6 C7 C8
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Note 3: C6 value equals recommended crystal load capacitance reduced by the PCB stray capacitances. Examples of crystal reference are given below (see characteristics on table 4) for different application bands: - at 315MHz band (freference= 9.84375MHz, -40C < TA < 85C): NDK LN-G102-950, - at 434/868MHz bands (freference= 13.56MHz, -40C < TA < 125C): NDK NX8045GB/CSJ S1-40125-8050-12 and NDK NX1255GA. Table 4: Typical crystal characteristics (SMD package) NDK NX8045GB/CSJ NDK LN-G102-950 NDK NX1255GA S1-40125-8050-12 (for 315MHz) (for 434MHz & 868MHz) (for 434MHz & 868MHz) 12 12 12 3.33 4.4 10.5 1.05 1.5 2.46 28 18.5 10
Parameter Load capacitance Motional capacitance Static capacitance Loss resistance
Unit pF fF pF
Figure 13 shows a two buttons keyfob board. Size is 30 x 45 millimeters. Figure 13: Two buttons keyfob board layout
COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION
Figure 14 gives a complete application schematic using a Motorola MC68HC908RK2 microcontroller. FSK modulation is selected, fcarrier= 433.92MHz. C1 capacitor can be removed if switch debounce is done by software.
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION
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Figure 14: .Application schematic for FSK modulation, serial configuration, 434MHz frequency band
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Note that for 868MHz band application, the input pin BAND must be wired to ground. See component description on table 5. Component Table 5: External components description for FSK Function Value 315MHz band: 9.84, see table 4 434MHz band: 13.56, Crystal see table 4 868MHz band: 13.56, see table 4 RF output level setting 12 resistor (Rext) Crystal load capacitor Power supply decoupling capacitor See table 6 22 100 Unit MHz MHz MHz k pF pF nF pF
Y1
R1 C3 C4 C2 C6
Figure 15 gives the corresponding PCB layout.
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MC33493 Technical Data
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RECOMMENDATIONS FOR FSK MODULATION
Figure 15: Application PCB layout for FSK modulation, serial configuration, 434MHz frequency band
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Table 6 gives the measured FSK deviations respective to C3 and C4 capacitor values for three deviations. Crystal reference is NDK NX8045GB/CSJ S1-40125-8050-12. Table 6 : Crystal pulling capacitor values versus carrier frequency total deviation -1Carrier frequency Carrier frequency C3 capacitor C4 capacitor Recommended (MHz) total deviation (kHz) (pF) (pF) R_off value (k) 45 4.7 6.8 10 434 70 2.2 10 100 1 15 22 90 4.7 6.8 10 868 140 2.2 10 200 1 15 22 Another crystal reference, NDK NX1255GA (see table 4), enables to reach higher deviation as mentioned on table 7. These results are due to the higher crystal motional capacitor. Table 7 : Crystal pulling capacitor values versus carrier frequency total deviation -2Carrier frequency Carrier frequency C3 capacitor C4 capacitor Recommended (MHz) total deviation (kHz) value (pF) value (pF) R_off value (k) 434 150 1 27 868 300 1 27 -
RECOMMENDATIONS FOR FSK MODULATION
FSK deviation is function of total load capacitance presented to the crystal. This load capacitance is constituted by various contributors: - the crystal characteristic, especially its static capacitance, - the external load capacitors (C3, C4 as defined in figure 14 and table 6), - the device internal capacitance of pins XTAL0, XTAL1, CFSK, - the PCB track capacitance. The schematic given in figure 16 shows a typical FSK application using serial capacitor configuration, where device pads and PCB track capacitances are mentioned. Device pad capacitance is defined by the package capacitance and by the internal circuitry. Typical capacitance values for these pads are given in table 8. Some realistic assumptions and measurements have been made concerning track parasitic capacitances for a 0.8mm FR4 double side application PCB. They are given in table 8 and the corresponding PCB layout is shown in figure 15. To achieve large deviations, this total load capacitance need to be lowered. For a given crystal, the PCB must be very carefully laid out in order to reduce as much as possible the capacitance of the tracks wired to XTAL0,
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RECOMMENDATIONS FOR FSK MODULATION XTAL1, CFSK pins.
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Recommendation: a R_off resistor can be added in parallel with the FSK switch to optimize the transient response of demodulated signal. Table 6 gives the optimized R_off values for two deviations. Note that there is no footprint for R_off resistor on the layout figure 15. When used, this component can be soldered on top of C3. Figure 16: Schematic detailing the crystal load capacitance contributors
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Table 8: Pads and tracks parasitic values Capacitance Value Unit C_pad_XTAL0 1 pF C_pad_XTAL1 1 pF C_pad_CFSK 1 pF C_track_XTAL0 1.5 pF C_track_XTAL1 1.5 pF C_track_CFSK 1.5 pF
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MC33493 Technical Data
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CASE OUTLINE DIMENSIONS
CASE OUTLINE DIMENSIONS
14X K REF
M 0.10 (0.004) T U S V S 0.15 (0.006)T U S N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT.
B -U1 7
N F DETAIL E K K1 J J1 SECTION N-N -W-
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0.15 (0.006)T U S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8
A -V-
C 0.10 (0.004) -T- SEATING D PLANE
G
H
DETAIL E
CASE 948G-01 ISSUE O
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MC33493/D
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